Logic Programming approaches for routing fault-free and maximally-parallel Wavelength Routed Optical Networks on Chip (Application paper)

One promising trend in digital system integration consists of boosting on-chip communication performance by means of silicon photonics, thus materializing the so-called Optical Networks-on-Chip (ONoCs). Among them, wavelength routing can be used to route a signal to destination by univocally associating a routing path to the wavelength of the optical carrier. Such wavelengths should be chosen so to minimize interferences among optical channels and to avoid routing faults. As a result, physical parameter selection of such networks requires the solution of complex constrained optimization problems. In previous work, published in the proceedings of the International Conference on Computer-Aided Design, we proposed and solved the problem of computing the maximum parallelism obtainable in the communication between any two endpoints while avoiding misrouting of optical signals. The underlying technology, only quickly mentioned in that paper, is Answer Set Programming (ASP). In this work, we detail the ASP approach we used to solve such problem. Another important design issue is to select the wavelengths of optical carriers such that they are spread across the available spectrum, in order to reduce the likelihood that, due to imperfections in the manufacturing process, unintended routing faults arise. We show how to address such problem in Constraint Logic Programming on Finite Domains (CLP(FD)). This paper is under consideration for possible publication on Theory and Practice of Logic Programming.Comment: Paper presented at the 33nd International Conference on Logic Programming (ICLP 2017), Melbourne, Australia, August 28 to September 1, 2017. 16 pages, LaTeX, 5 figure

Bottom-Up Abstract Modelling of Optical Networks-on-Chip: From Physical to Architectural Layer

This work presents a bottom-up abstraction procedure based on the design-flow FDTD + SystemC suitable for the modelling of optical Networks-on-Chip. In this procedure, a complex network is decomposed into elementary switching elements whose input-output behavior is described by means of scattering parameters models. The parameters of each elementary block are then determined through 2D-FDTD simulation, and the resulting analytical models are exported within functional blocks in SystemC environment. The inherent modularity and scalability of theS-matrix formalism are preserved inside SystemC, thus allowing the incremental composition and successive characterization of complex topologies typically out of reach for full-vectorial electromagnetic simulators. The consistency of the outlined approach is verified, in the first instance, by performing a SystemC analysis of a four-input, four-output ports switch and making a comparison with the results of 2D-FDTD simulations of the same device. Finally, a further complex network encompassing 160 microrings is investigated, the losses over each routing path are calculated, and the minimum amount of power needed to guarantee an assigned BER is determined. This work is a basic step in the direction of an automatic technology-aware network-level simulation framework capable of assembling complex optical switching fabrics, while at the same time assessing the practical feasibility and effectiveness at the physical/technological level

Error Control Schemes for On-chip Communication Links: the energy-reliability trade-off

On-chip interconnection networks for future systems on chip (SoC) will have to deal with the increasing sensitivity of global wires to noise sources such as crosstalk or power supply noise. Hence, transient delay and logic faults are likely to reduce the reliability of across-chip communication. Given the reduced power budgets for SoCs, in this paper, we develop solutions for combined energy minimization and communication reliability control. Redundant bus coding is proved to be an effective technique for trading off energy against reliability, so that the most efficient scheme can be selected to meet predefined reliability requirements in a low signal-to-noise ratio regime. We model on-chip interconnects as noisy channels and evaluate the impact of two error recovery schemes on energy efficiency: correction at the receiver stage versus retransmission of corrupted data. The analysis is performed in a realistic SoC setting, and holds both for shared communication resources and for peer-to-peer links in a network of interconnects. We provide SoC designers with guidelines for the selection of energy efficient error-control schemes for communication architectures

NoC Synthesis Flow for Customized Domain Specific Mutliprocessor Systems-on-Chip

The growing complexity of customizable single-chip multiprocessors is requiring communication resources that can only be provided by a highly-scalable communication infrastructure. This trend is exemplified by the growing number of network-on-chip (NoC) architectures that have been proposed recently for system-on-chip (SoC) integration. Developing NoC-based systems tailored to a particular application domain is crucial for achieving high-performance, energy-efficient customized solutions. The effectiveness of this approach largely depends on the availability of an ad hoc design methodology that, starting from a high-level application specification, derives an optimized NoC configuration with respect to different design objectives and instantiates the selected application specific on-chip micronetwork. Automatic execution of these design steps is highly desirable to increase SoC design productivity. This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler). The entire flow leverages the flexibility of a fully reusable and scalable network components library called xpipes, consisting of highly-parameterizable network building blocks (network interface, switches, switch-to-switch links) that are design-time tunable and composable to achieve arbitrary topologies and customized domain-specific NoC architectures. Several experimental case studies are presented In the work, showing the powerful design space exploration capabilities of the proposed methodology and tools

Benefit-risk profile of cytoreductive drugs along with antiplatelet and antithrombotic therapy after transient ischemic attack or ischemic stroke in myeloproliferative neoplasms

We analyzed 597 patients with myeloproliferative neoplasms (MPN) who presented transient ischemic attacks (TIA, n = 270) or ischemic stroke (IS, n = 327). Treatment included aspirin, oral anticoagulants, and cytoreductive drugs. The composite incidence of recurrent TIA and IS, acute myocardial infarction (AMI), and cardiovascular (CV) death was 4.21 and 19.2%, respectively at one and five years after the index event, an estimate unexpectedly lower than reported in the general population. Patients tended to replicate the first clinical manifestation (hazard ratio, HR: 2.41 and 4.41 for recurrent TIA and IS, respectively); additional factors for recurrent TIA were previous TIA (HR: 3.40) and microvascular disturbances (HR: 2.30); for recurrent IS arterial hypertension (HR: 4.24) and IS occurrence after MPN diagnosis (HR: 4.47). CV mortality was predicted by age over 60 years (HR: 3.98), an index IS (HR: 3.61), and the occurrence of index events after MPN diagnosis (HR: 2.62). Cytoreductive therapy was a strong protective factor (HR: 0.24). The rate of major bleeding was similar to the general population (0.90 per 100 patient-years). In conclusion, the long-term clinical outcome after TIA and IS in MPN appears even more favorable than in the general population, suggesting an advantageous benefit-risk profile of antithrombotic and cytoreductive treatment

Prevalence and associated factors of COVID-19 across Italian regions: a secondary analysis from a national survey on physiotherapists

Coronavirus disease 2019 (COVID-19) broke out in China in December 2019 and now is a pandemic all around the world. In Italy, Northern regions were hit the hardest during the first wave. We aim to explore the prevalence and the exposure characteristics of physiotherapists (PTs) working in different Italian regions during the first wave of COVID-19

Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers

NAND flash memories are becoming the predominant technology in the implementation of mass storage systems for both embedded and high-performance applications. However, when considering data and code storage in non-volatile memories (NVMs), such as NAND flash memories, reliability and performance be- come a serious concern for systems' designer. Designing NAND flash based systems based on worst-case scenarios leads to waste of resources in terms of performance, power consumption, and storage capacity. This is clearly in contrast with the request for run-time reconfigurability, adaptivity, and resource optimiza- tion in nowadays computing systems. There is a clear trend toward supporting differentiated access modes in flash memory controllers, each one setting a differentiated trade-off point in the performance-reliability optimization space. This is supported by the possibility of tuning the NAND flash memory performance, reli- ability and power consumption acting on several tuning knobs such as the flash programming algorithm and the flash error correcting code. However, to successfully exploit these degrees of freedom, it is mandatory to clearly understand the effect the combined tuning of these parameters have on the full NVM sub-system. This paper performs a comprehensive quantitative analysis of the benefits provided by the run-time reconfigurability of an MLC NAND flash controller through the combined effect of an adaptable memory programming circuitry coupled with run-time adaptation of the ECC correction capability. The full non- volatile memory (NVM) sub-system is taken into account, starting from the characterization of the low level circuitry to the effect of the adaptation on a wide set of realistic benchmarks in order to provide the readers a clear figure of the benefit this combined adaptation would provide at the system leve

DNA topoisomerase I inhibition by camptothecin induces escape of RNA polymerase II from promoter-proximal pause site, antisense transcription and histone acetylation at the human HIF-1α gene locus

Top1 inhibition by camptothecin (CPT) perturbs RNA polymerase II (Pol II) density at promoters and along transcribed genes suggesting an involvement of Top1 in Pol II pausing. Here, we demonstrate that Top1 inhibition favors Pol II escape from a promoter-proximal pausing site of the human HIF-1α gene in living cells. Interestingly, alternative splicing at exon 11 was markedly altered in nascent HIF-1α mRNAs, and chromatin structure was also affected with enhanced histone acetylation and reduced nucleosome density in a manner dependent on cdk activity. Moreover, CPT increases transcription of a novel long RNA (5′aHIF1α), antisense to human HIF-1α mRNA, and a known antisense RNA at the 3′-end of the gene, while decreasing mRNA levels under normoxic and hypoxic conditions. The effects require Top1, but are independent from Top1-induced replicative DNA damage. Chromatin RNA immunoprecipitation results showed that CPT can activate antisense transcription mediated by cyclin-dependent kinase (cdk) activity. Thus, Top1 inhibition can trigger a transcriptional stress, involving antisense transcription and increased chromatin accessibility, which is dependent on cdk activity and deregulated Pol II pausing. A changed balance of antisense transcripts and mRNAs may then lead to altered regulation of HIF-1α activity in human cancer cells

Prescription appropriateness of anti-diabetes drugs in elderly patients hospitalized in a clinical setting: evidence from the REPOSI Register

Diabetes is an increasing global health burden with the highest prevalence (24.0%) observed in elderly people. Older diabetic adults have a greater risk of hospitalization and several geriatric syndromes than older nondiabetic adults. For these conditions, special care is required in prescribing therapies including anti- diabetes drugs. Aim of this study was to evaluate the appropriateness and the adherence to safety recommendations in the prescriptions of glucose-lowering drugs in hospitalized elderly patients with diabetes. Data for this cross-sectional study were obtained from the REgistro POliterapie-Società Italiana Medicina Interna (REPOSI) that collected clinical information on patients aged ≥ 65 years acutely admitted to Italian internal medicine and geriatric non-intensive care units (ICU) from 2010 up to 2019. Prescription appropriateness was assessed according to the 2019 AGS Beers Criteria and anti-diabetes drug data sheets.Among 5349 patients, 1624 (30.3%) had diagnosis of type 2 diabetes. At admission, 37.7% of diabetic patients received treatment with metformin, 37.3% insulin therapy, 16.4% sulfonylureas, and 11.4% glinides. Surprisingly, only 3.1% of diabetic patients were treated with new classes of anti- diabetes drugs. According to prescription criteria, at admission 15.4% of patients treated with metformin and 2.6% with sulfonylureas received inappropriately these treatments. At discharge, the inappropriateness of metformin therapy decreased (10.2%, P < 0.0001). According to Beers criteria, the inappropriate prescriptions of sulfonylureas raised to 29% both at admission and at discharge. This study shows a poor adherence to current guidelines on diabetes management in hospitalized elderly people with a high prevalence of inappropriate use of sulfonylureas according to the Beers criteria